The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

May. 15, 2025
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventor:

Se Hyun Lee, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0819 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2330/021 (2013.01); G09G 2330/028 (2013.01); G09G 2340/0457 (2013.01);
Abstract

A sub-pixel includes a first transistor including a first electrode connected to a third node, a second electrode connected to a first node, and a gate electrode connected to a second node, a second transistor including a first electrode connected to the second node, a second electrode electrically connected to one of a plurality of data lines, and a gate electrode electrically connected to a first sub-gate line, a fourth transistor including a first electrode electrically connected to a third power line, a second electrode connected to the third node, and a gate electrode electrically connected to a second sub-gate line, a third capacitor including an electrode connected to the gate electrode of the fourth transistor and another electrode connected to the second node, and a fourth capacitor including an electrode connected to the gate electrode of the second transistor and another electrode connected to the second node.


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