System and method for cumulative latency voting mode for dcvs

Abstract

Systems, methods, and devices of the various embodiments provide managing an active clock frequency of a processor, including determining a preconfigured minimum clock frequency and a preconfigured maximum clock frequency using a first set of operating parameters of a first processing task and a second set of operating parameters of a second processing task, initiating execution of the first and the second processing tasks utilizing a DCVS framework using a current clock frequency equal to a target clock frequency, accumulating a first latency value and a second latency value and determining a steady state latency based on the first and second latency values, determining whether the steady state latency satisfies a target frame rate, and adjusting the current clock frequency in response to the determination that either the first steady state latency or the second steady state latency fails to satisfy the target frame rate.