The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Apr. 14, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young Kun Jee, Suwon-si, KR;

Sanghoon Lee, Suwon-si, KR;

Un-Byoung Kang, Suwon-si, KR;

Sang Cheon Park, Suwon-si, KR;

Jumyong Park, Suwon-si, KR;

Hyunchul Jung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/768 (2006.01); H10W 20/00 (2026.01); H10W 20/20 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/023 (2026.01); H10W 20/20 (2026.01); H10W 74/117 (2026.01); H10W 72/019 (2026.01); H10W 90/297 (2026.01); H10W 90/792 (2026.01);
Abstract

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.


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