The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jan. 12, 2023
Applicant:

Meta Platforms, Inc., Menlo Park, CA (US);

Inventors:

Ravi Shankar Agarwal, Los Altos, CA (US);

Kaushal Gandhi, South San Francisco, CA (US);

Bhasker Reddy Jakka, Fremont, CA (US);

Harikrishna Madadi Reddy, San Jose, CA (US);

Baheerathan Anandharengan, Milpitas, CA (US);

Christian Markus Petersen, Golden, CO (US);

Olivia Wu, Los Altos, CA (US);

Mahesh Srinivasa Maddury, San Jose, CA (US);

Pankaj Kansal, Fremont, CA (US);

Assignee:

META PLATFORMS, INC., Menlo Park, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.01); H10W 20/20 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 20/20 (2026.01); H10W 72/952 (2026.01); H10W 90/792 (2026.01);
Abstract

Three-dimensional application specific integrated circuit (IC) architecture is described herein. In one aspect, an IC may include a first die including: a first semiconductor layer; a plurality of processing elements (PEs) located on the first semiconductor layer; and a first interface region of the first semiconductor layer, electrically coupled to the plurality of PEs and configured to communicate electrical signals with the plurality of PEs; a second die including: a second semiconductor layer; a plurality of IC elements located on the second semiconductor layer; and a second interface region of the second semiconductor layer, electrically coupled to the plurality of IC elements and configured to communicate electrical signals to the plurality of IC elements, where the first interface region and the second interface region are electrically coupled to each other and configured to transmit electrical signals between the plurality of PEs and the plurality of IC elements.


Find Patent Forward Citations

Loading…