The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Mar. 25, 2022
Applicant:

Lg Innotek Co., Ltd., Seoul, KR;

Inventors:

Tae Gyu Kang, Seoul, KR;

Dong Keon Lee, Seoul, KR;

Won Suk Jung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H10B 80/00 (2023.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 90/28 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10B 80/00 (2023.02); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 90/28 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package according to an embodiment includes a first substrate layer; and a second substrate layer disposed on the first substrate layer, wherein the first substrate layer includes at least one first insulating layer; a first circuit pattern disposed on the first insulating layer; and a first via passing through the first insulating layer and connected to the first circuit pattern, wherein the second substrate layer includes a second insulating layer disposed on the first insulating layer; a second circuit pattern disposed on the second insulating layer; and a second via passing through the second insulating layer and connected to the second circuit pattern, wherein the first insulating layer and the second insulating layer include different insulating materials and wherein a width of the first via is different from a width of the second via.


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