The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

May. 11, 2023
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Sung Ju Choi, Paju-si, KR;

Jung Seok Seo, Paju-si, KR;

Jae Yoon Park, Paju-si, KR;

Seo Yeon Im, Paju-si, KR;

Jin Won Jung, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/121 (2023.01); H10D 30/67 (2025.01); H10K 59/126 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10D 30/6723 (2025.01); H10D 30/6729 (2025.01); H10D 30/673 (2025.01); H10D 30/6745 (2025.01); H10D 30/6755 (2025.01); H10K 59/1216 (2023.02); H10K 59/126 (2023.02);
Abstract

An organic light emitting display device including a substrate, a light emitting element on the substrate, and a driving thin film transistor supplying drive current to the light emitting element is disclosed. The driving thin film transistor includes a buffer layer on the substrate, a first polycrystalline silicon semiconductor layer on the buffer layer, a first oxide semiconductor layer contacting the first polycrystalline silicon semiconductor layer while being disposed thereon and including a first channel region, a first source region, and a first drain region, a gate insulating layer covering the first oxide semiconductor layer and the first polycrystalline silicon semiconductor layer, a first gate electrode disposed on the gate insulating layer, a first source electrode connected to the first source region, a first drain electrode connected to the first drain region, and a first light shielding layer disposed under the first oxide semiconductor layer while overlapping therewith.


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