The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Mar. 23, 2023
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Kyong-Chol Lee, Yongin-si, KR;

Yunjong Yeo, Yongin-si, KR;

Taesung Kim, Yongin-si, KR;

Hyunmin Cho, Yongin-si, KR;

Yeonhong Kim, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/121 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10D 30/031 (2025.01); H10D 30/673 (2025.01); H10D 30/6736 (2025.01); H10D 30/6755 (2025.01); H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/431 (2025.01); H10D 86/60 (2025.01); H10K 59/1201 (2023.02); H10K 71/00 (2023.02);
Abstract

A display device includes a first transistor including a first active pattern including a first oxide semiconductor, and a first gate electrode which is on the first active pattern, a second transistor including a second active pattern including a second oxide semiconductor different from the first oxide semiconductor, and a second gate electrode which is on the second active pattern, a first gate insulating pattern between the second active pattern and the second gate electrode, a second gate insulating pattern facing the first gate insulating pattern with the second active pattern therebetween, and a third gate insulating pattern between the first active pattern and the first gate electrode, the third gate insulating pattern directly contacting the first active pattern and the first gate electrode.


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