The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jun. 06, 2023
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Remy Berthelon, Crolles, FR;

Olivier Weber, Grenoble, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/26 (2006.01); H01L 21/321 (2006.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10B 63/10 (2023.01);
U.S. Cl.
CPC ...
H10D 62/115 (2025.01); H01L 21/3212 (2013.01); H01L 21/76229 (2013.01); H10B 63/10 (2023.02);
Abstract

The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.


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