The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Sep. 19, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Beom Seo Kim, Suwon-si, KR;

Bo Ram Gu, Namyangju-si, KR;

Ja Min Koo, Hwaseong-si, KR;

Sung Gil Kim, Yongin-si, KR;

Jong Hyeok Kim, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H10B 12/315 (2023.02); G11C 5/063 (2013.01); H10B 12/31 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02);
Abstract

A semiconductor memory device includes a substrate including an active area defined by an element separation layer, the active area including a first portion and second portions defined on both sides of the first portion a bit line crossing the active area and extending in a first direction on the substrate, and a bit line contact disposed between the substrate and the bit line and directly connected to the first portion of the active area. The bit line contact includes an indent area recessed into the substrate and an upper area on the indent area, a width of the indent area decreases as a distance from the bit line increases, the indent area includes a slope forming a boundary with the substrate and having a straight line shape, and a starting point of the slope of the indent area is lower than an upper surface of the element separation layer.


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