The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Feb. 29, 2024
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Paul Zavalney, Austin, TX (US);

Tak Ying Wong, Singapore, SG;

Harikrishnan Prabha Valsala, Singapore, SG;

Pio Balmelli, Arogno, CH;

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03K 5/14 (2014.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0033 (2013.01); H03K 5/14 (2013.01); H03K 2005/00078 (2013.01);
Abstract

In one aspect, an apparatus includes: a delay line to receive a clock signal and a plurality of settings, each of the settings to indicate a selected tap of the delay line at which to output the clock signal. The delay line is to output a capture clock based on a first setting, and monitor clocks based on additional settings. The apparatus also includes: a data sampler to sample incoming data with the capture clock and output capture data; monitor samplers to sample the incoming data with the monitor clocks and output monitored data; and a monitor circuit to trigger an update to at least one of the settings based on comparison of the capture data to the monitored data.


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