The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jun. 05, 2024
Applicant:

Alpha and Omega Semiconductor International Lp, Ontario, CA;

Inventors:

Hao Peng, San Jose, CA (US);

Ziwei Yu, Cupertino, CA (US);

Sitthipong Angkititrakul, Dublin, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/125 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 5/125 (2013.01); H03K 3/037 (2013.01); H03K 2005/00078 (2013.01); H03K 19/20 (2013.01);
Abstract

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.


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