Authentication code generation/checking instructions

Abstract

An apparatus comprises processing circuitry to execute instructions, and decode circuitry to decode the instructions for execution by the processing circuitry. The decode circuitry is responsive to an authentication code generation instruction specifying a first source value to control the processing circuitry to generate an authentication code dependent on the first source value, and store the authentication code to a memory location associated with a store address formed using a value obtained from a register. By providing a single instruction, this reduces register pressure enabling improved performance by avoiding unnecessary load/store operations, and makes compilation of code using the authentication code generation instruction simpler. Because it does not store the result of the cryptographic function in the register bank, it also enables simple in-order CPU designs to hide the latency of slow cryptographic computations by allowing subsequent instructions to start executing before the cryptographic computation has completed.