The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jan. 09, 2024
Applicants:

Xilinx, Inc., San Jose, CA (US);

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Chuan Cheng Pan, San Jose, CA (US);

Jaideep Dastidar, Austin, TX (US);

David James Riddoch, Cambridgeshire, GB;

Andrew Jackson, Cambridge, GB;

Anujan Varma, Cupertino, CA (US);

James Anderson, Madison, AL (US);

Assignees:

XILINX, INC., San Jose, CA (US);

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 13/4221 (2013.01); G06F 9/30101 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45587 (2013.01);
Abstract

Embodiments herein describe a circuit including a user domain configured to execute user functions and a hardened domain configured to communicate with the user domain. The hardened domain includes peripheral component interconnect express (PCIe) function decoding logic having a plurality of register bits and a Trusted Execution Environment (TEE) Device Interface Security Protocol (TDISP) core communicating with the PCIe function decoding logic. The TDISP core supports a plurality of PCIe functions. Each register bit of the plurality of register bits is assigned to a respective PCIe function of the plurality of PCIe functions.


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