Processor and method for memory access instruction, and electronic device

Abstract

The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.