The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jun. 29, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Takeshi Aoki, Ebina, JP;

Yoshiyuki Kurokawa, Sagamihara, JP;

Munehiro Kozuma, Atsugi, JP;

Takuro Kanemura, Sapporo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/544 (2006.01); G06F 15/78 (2006.01); G11C 11/40 (2006.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
G06F 7/5443 (2013.01); G06F 15/7821 (2013.01); G11C 11/40 (2013.01); H10D 30/6755 (2025.01);
Abstract

A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.


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