The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jul. 24, 2024
Applicant:

Nvidia Corp., Santa Clara, CA (US);

Inventors:

Alon Amid, Haifa, IL;

Aleksandr Frid, San Francisco, CA (US);

Ben Pei En Tsai, Helsinki, FI;

Alon Sadan, Zichron Yaakov, IL;

Assignee:

NVIDIA Corp., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 1/28 (2006.01); G06F 1/3203 (2019.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/28 (2013.01); G06F 1/3203 (2013.01); G11C 16/30 (2013.01);
Abstract

Systems including a power supply and multiple chips or die, wherein settings may be configured that when applied to a first one of the chips or die configure the first chip or die to associate a power allocation limit with at least a second one of the chips or die, wherein a sum of the power allocation limit and a power consumption limit of the first chip or die exceeds a total power capacity of the power supply. The systems operate the first chip or die at a lower priority than the other chips or die for receiving operating power from the power supply, and the first chip or die is operated as a master controller of allocation of the operating power from the power supply to the first chip or die and to the other chips or die.


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