The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jun. 10, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Bharat Kumar Rangarajan, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/04 (2006.01); G06F 1/18 (2026.01); G06F 1/3203 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 9/4401 (2018.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/04 (2013.01); G06F 1/189 (2013.01); G06F 1/263 (2013.01); G06F 1/3203 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 9/4418 (2013.01); G06F 12/0897 (2013.01);
Abstract

Aspects disclosed in the detailed description include a heterogenous processor-based system for dynamically coupling power and clock to a last level cache. The heterogenous processor-based system includes a processing cluster of big cores and little cores. The big cores are coupled to a big core power rail to power its operations. The little cores are coupled to a little core power rail to power its operations. The plurality of big and little cores share a last level cache to read data from and write data to. The heterogenous processor-based system is configured to determine whether each of the big cores and little cores are active or inactive. In response to determining that all the big cores are inactive and at least one of the plurality of little cores is active, the processor-based system configured to dynamically couple the little core power rail to the last level cache.


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