The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Apr. 19, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Changeun Joo, Suwon-si, KR;

Ohguk Kwon, Suwon-si, KR;

Sunjae Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06568 (2013.01);
Abstract

A semiconductor package may include a first redistribution substrate, a second redistribution substrate on the first redistribution substrate, a chip stack between the first redistribution substrate and the second redistribution substrate, a first molding layer on the chip stack, and a through electrode extending into the first molding layer and electrically connecting the first redistribution substrate to the second redistribution substrate. The chip stack may include a first semiconductor chip on the first redistribution substrate, the first semiconductor chip including a through via that extends therein, a chip structure including a second semiconductor chip and a second molding layer, the second semiconductor chip being on the first semiconductor chip and electrically connected to the through via, and a third semiconductor chip between the chip structure and the second redistribution substrate, and a side surface of the first semiconductor chip may be coplanar with a side surface of the chip structure.


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