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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12635575 B1

PDFFull Text
Date of Patent:
May. 19, 2026

Filed:

Oct. 12, 2021

Semiconductor device comprising a stack of chips, and chips for such a stack

Applicant:

Qualcomm Technologies, Inc., San Diego, CA (US);

Inventor:

Fabrice Devaux, Lausanne, CH;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:

Withrow & Terranova, PLLC

Primary Examiner:

Kretelia Graham

Assistant Examiner:

William Henry Anderson

Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/44 (2006.01); H01L 23/46 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H10B 80/00 (2023.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 40/00 (2026.01); H10W 70/63 (2026.01); H10W 90/00 (2026.01); H10W 40/30 (2026.01); H10W 40/40 (2026.01); H10W 90/20 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 20/42 (2026.01); H10W 20/435 (2026.01); H10W 40/00 (2026.01); H10W 70/635 (2026.01); H10W 90/701 (2026.01); H10W 40/30 (2026.01); H10W 40/40 (2026.01); H10W 90/24 (2026.01); H10W 90/288 (2026.01); H10W 90/297 (2026.01);
Abstract

The invention relates to a semiconductor device () comprising a stack of chips (C; C) arranged in successive levels along a stacking direction, each chip extending in a main plane perpendicular to the stacking direction. The stack (E) comprises a plurality of chips (C) of a first type comprising a first portion (P) and a second portion (P) each extending in the main plane, the first portion (P) being liable to release more heat than the second portion (P) when the chip is operating. Each chip of the first type (C) is arranged in mechanical contact with a chip in an adjacent level of the stack (E) by way of a stacking surface that extends only over its second portion (P), such that its first portion (P) forms a projecting part able to be exposed to a cooling fluid.

Find Patent Forward Citations

Devaux, Fabrice. (2026). Semiconductor device comprising a stack of chips, and chips for such a stack (U.S. Patent No. 12635575). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12635575

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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