The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Nov. 20, 2022
Applicant:

Novatek Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Tsung-Ling Li, Hsinchu County, TW;

Yung-Cheng Lin, Hsinchu County, TW;

Ju-Lin Huang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/044 (2006.01); G06F 3/041 (2006.01); H01L 23/498 (2006.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); G06F 3/0412 (2013.01); G06F 3/04164 (2019.05); G06F 3/0446 (2019.05); H10W 90/701 (2026.01);
Abstract

A ball grid array (BGA) package for use in a touch panel controller includes a package substrate and a plurality of solder bumps. The plurality of solder bumps are disposed on the package substrate, arranged in a staggered pattern surrounding a hollow region on the package substrate, and coupled to electrodes of a touch panel via a multi-layer circuit board. The staggered pattern includes Ys1 top rows and Ys2 bottom rows, a minimum vertical distance between centers of two vertically adjacent solder bumps in the Ys1 top rows and the Ys2 bottom rows being referred to as an equivalent vertical pitch, and Ys1, Ys2 being integers exceeding 2. the hollow region has a minimum length defined by the minimum length=((Ys1−2)+(Ys2−2))*the equivalent vertical pitch.


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