The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Oct. 26, 2022
Applicant:

Sharp Display Technology Corporation, Kameyama City, JP;

Inventors:

Masahiko Suzuki, Kameyama City, JP;

Tetsuo Kikuchi, Kameyama City, JP;

Setsuji Nishimiya, Kameyama City, JP;

Kengo Hara, Kameyama City, JP;

Hitoshi Takahata, Kameyama City, JP;

Tohru Daitoh, Kameyama City, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/60 (2025.01); H10D 86/40 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); H10D 86/441 (2025.01);
Abstract

An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer. The plurality of oxide semiconductor TFTs include a first TFT including an oxide semiconductor layer extending across the first gate wiring line and the second gate wiring line in the column direction, when viewed from a normal direction of the substrate. Portions of the first gate wiring line and the second gate wiring line, over which the oxide semiconductor layer of the first TFT extends, respectively function as the lower gate electrode and the upper gate electrode of the first TFT. When viewed from the normal direction of the substrate, the first gate wiring line includes a plurality of first notched portions disposed spaced apart from each other and a first solid portion, the first solid portion being a portion other than the plurality of first notch portions. When viewed from the normal direction of the substrate, the second gate wiring line includes a second solid portion including a plurality of first overlapping portions disposed spaced apart from each other, each of the first overlapping portions partially overlapping at least one of the plurality of first notched portions, and a second overlapping portion overlapping the first solid portion. When viewed from the normal direction of the substrate, the second overlapping portion continuously extends from one of two of the plurality of source wiring lines adjacent to each other, to the other of the two source wiring lines adjacent to each other.


Find Patent Forward Citations

Suzuki, Masahiko. (2026). Active matrix substrate (U.S. Patent No. 12635243). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12635243

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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