The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Dec. 05, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yeojin Na, Hwaseong-si, KR;

Juyun Park, Seongnam-si, KR;

Jongdoo Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01);
Abstract

A method of designing a layout of a semiconductor device includes forming a second layout by analyzing a first layout and correcting at least a portion of a plurality of filler cells, wherein the forming the second layout includes detecting transition regions due to a difference in width by respectively comparing a first width of a first active line and a second width of a second active line with a width of a dummy active line, in the first layout; and correcting the dummy active line of the first filler cell by analyzing the detected transition regions, wherein, in the correcting the dummy active line of the first filler cell, the dummy active line is corrected to be a corrected dummy active line having the same width as an active line having a narrower width, among the first and second active lines.


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