The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Aug. 19, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minseob Lee, Suwon-si, KR;

Sangmin Yoo, Suwon-si, KR;

Joonhee Lee, Suwon-si, KR;

Ikkyun Jo, Suwon-si, KR;

Honggul Han, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/197 (2006.01); H03L 7/097 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03L 7/097 (2013.01); H03L 7/099 (2013.01);
Abstract

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.


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