The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2026
Filed:
Feb. 02, 2024
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Avri Harush, Herzliya, IL;
Oleg Dadashev, Hadera, IL;
Assignee:
Infineon Technologies Americas Corp., El Segundo, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/089 (2006.01); H03K 5/156 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/089 (2013.01); H03K 5/1565 (2013.01); H03L 7/093 (2013.01); H03L 7/0995 (2013.01);
Abstract
Technologies directed to phase-locked loop (PLL) duty cycle calibration are described. A circuit includes an amplifier to generate a level-shifted clock with a duty cycle. The circuit further includes comparison logic coupled to an output of the amplifier that compares the duty cycle to a target duty cycle and generates a difference value. Tuning logic coupled to the amplifier adjust the duty cycle based on the difference value.