The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Oct. 24, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jinho Kim, Suwon-si, KR;

Donggun Oh, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); H10D 86/451 (2025.01); H10D 86/60 (2025.01); H10W 90/00 (2026.01); G09G 2300/0426 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0626 (2013.01); H10D 86/441 (2025.01);
Abstract

A display module is disclosed. The present display module comprises: a driving circuit layer provided on a substrate and comprising first driving circuits and second driving circuits; and a pixel array provided on the driving circuit layer and having pixels arranged in a matrix, the pixels each including a plurality of inorganic light-emitting devices, wherein: the first driving circuits provided for each pixel drive the plurality of inorganic light-emitting devices included in each pixel on the basis of data voltages applied through data lines; the second driving circuits generate control signals for driving the first driving circuits on the basis of clock signals applied through clock lines and provide same to the first driving circuits; the driving circuit layer comprises a first metal layer, a second metal layer, and at least one third metal layer; and the clock signals are applied from the clock lines to the second driving circuits through jumping lines formed in one of the at least one third metal layer.


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