The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Nov. 02, 2021
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Sundeep Amirineni, Cedar Park, TX (US);

Paul Gilbert Meyer, Jericho, VT (US);

Ron Diamant, San Jose, CA (US);

Qingrui Liu, Burlingame, CA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/78 (2006.01); G06F 12/0802 (2016.01); G06F 17/16 (2006.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 7/78 (2013.01); G06F 12/0802 (2013.01); G06F 17/16 (2013.01);
Abstract

A processing engine array is provided with an interconnect mode of operation to use the array as an interconnect to move data elements to different locations in memory such as to perform a matrix transpose operation. In this interconnect mode of operation, although computations are still being performed in the array, the computations are not carried out to modify or change the values of the data elements, but are instead carried out to rearrange the data elements in memory. As such, the computations carried out in the interconnect mode of operation can deviate from the expected behavior of floating-point calculations. A mode selection signal can be used to provide the proper outputs of the processing elements of the array depending on the mode of operation.


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