The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

May. 30, 2023
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Saurabh Shrivastava, Saratoga, CA (US);

Nidhi Patel, Fremont, CA (US);

Geethanjali Rajegowda, San Jose, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/04 (2013.01);
Abstract

A method includes receiving one or more configuration parameters associated with a neural processing unit (NPU), wherein the one or more configuration parameters defines a number of processing tiles within the NPU, and wherein a processing tile includes a processing element of a first type configured to perform a dense operation, a processing element of a second type configured to perform a sparse operation, and an on-chip memory (OCM) associated therewith; and automatically generating the NPU based on the one or more configuration parameters and further based on a hardware descriptive language (HDL).


Find Patent Forward Citations

Shrivastava, Saurabh. (2026). Method and system to configure a neural processing unit (U.S. Patent No. 12632697). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12632697

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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