Prefetch request generation

Abstract

An apparatus has decoding circuitry to decode instructions defined according to an instruction set architecture (ISA) support a loop control instruction providing an explicit loop presence hint indicating that a sequence of instructions to be executed includes a program loop body to be iterated. Processing circuitry performs data processing in response to the decoded instructions. Prefetch circuitry generates a prefetch request for data to be prefetched into a cache corresponding to an address predicted to be accessed by the processing circuitry in future. In response to determining that the decoding circuitry has detected the loop control instruction, the prefetch circuitry activates generation of at least one loop-control-instruction-triggered stream of prefetch requests specifying addresses predicted based on a property of at least one instruction of the program loop body whose presence is indicated by the loop control instruction.