The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Apr. 19, 2021
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Justin Stekli, Dayton, OH (US);

Bathrinarayanan Mukundan, Bengaluru, IN;

Ryan Christopher Jones, Evendale, OH (US);

Paul C. Schilling, West Chester, OH (US);

Assignee:

General Electric Company, Evendale, OH (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B29C 64/386 (2017.01); B33Y 50/00 (2015.01); G05B 19/4099 (2006.01); G06F 30/10 (2020.01); G06F 113/10 (2020.01);
U.S. Cl.
CPC ...
B29C 64/386 (2017.08); B33Y 50/00 (2014.12); G05B 19/4099 (2013.01); G06F 30/10 (2020.01); G05B 2219/35134 (2013.01); G05B 2219/49023 (2013.01); G06F 2113/10 (2020.01);
Abstract

A printing device receives modeling data that defines a three-dimensional solid model of a component body having a plurality of faces and a plurality of edges. Each of the faces meets another face of the component body at a respective edge of the component body. The printing device interrogates one or more faces of the component body to identify one or more looped geometries, and defines a lattice exclusion area having a boundary formed based at least in part on one or more faces of the component body that correspond to the looped geometries. The printing device generates a printer output of the component body and a lattice support structure for the component body. The printer output of the lattice support structure is outside of the lattice exclusion area.


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