The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Oct. 06, 2023
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Takamichi Hosokawa, Tokyo, JP;

Tatsuaki Tsukuda, Tokyo, JP;

Yoshihiro Masumura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01F 17/00 (2006.01); H01F 19/04 (2006.01); H01F 38/16 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01F 17/0006 (2013.01); H01L 23/3107 (2013.01); H01L 23/49503 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/48245 (2013.01);
Abstract

A semiconductor device includes: a first chip mounting portion and a second chip mounting portion adjacent to each other in a first direction; a first semiconductor chip and a third semiconductor chip adjacent to each other in a second direction and mounted on the first chip mounting portion; and a second semiconductor chip mounted on the second chip mounting portion. The third semiconductor has: one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip. In plan view, the first and second transformers are arranged along a side facing the second semiconductor chip, and the one of more first transformers are arranged closer to the first semiconductor chip than the one of more second transformers.


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