The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Nov. 02, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyungsoo Kim, Suwon-si, KR;

Kyenhee Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/481 (2013.01); H01L 23/49844 (2013.01); H01L 23/5384 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/07 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/16146 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.


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