The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Feb. 14, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Myungsam Kang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 21/4853 (2013.01); H01L 23/5386 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H10B 80/00 (2023.02); H01L 2224/11825 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13562 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/14361 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.


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