The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Feb. 20, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mustafa Badaroglu, San Diego, CA (US);

Zhongze Wang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 80/00 (2026.01); H10W 20/20 (2026.01); H10W 20/41 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H10W 20/20 (2026.01); H10W 20/427 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 72/07252 (2026.01); H10W 72/07254 (2026.01); H10W 72/227 (2026.01); H10W 72/247 (2026.01); H10W 72/922 (2026.01); H10W 72/926 (2026.01); H10W 72/942 (2026.01); H10W 72/944 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01);
Abstract

A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.


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