The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Jan. 29, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Mikio Oka, Kanagawa, JP;

Kazuki Yamaguchi, Kumamoto, JP;

Masashi Kino, Kumamoto, JP;

Takashige Doi, Kanagawa, JP;

Masashige Moritoki, Kumamoto, JP;

Takashi Watanabe, Kumamoto, JP;

Norikazu Kasahara, Kumamoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 48/40 (2025.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01);
U.S. Cl.
CPC ...
H10B 61/22 (2023.02); G11C 11/161 (2013.01);
Abstract

A memory cell array of the present disclosure includes a plurality of memory cellsarranged in a first direction and a second direction different from the first direction. Each of the memory cellsincludes a resistance-variable nonvolatile memory element and a selection transistor TR electrically connected to the nonvolatile memory element. The selection transistor TR is formed in an active regionprovided in a semiconductor layer. At least a part of the active regionis in contact with an element isolation regionprovided in the semiconductor layer. A surface of the element isolation regionis located at a position lower than a surface of the active region


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