The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Feb. 12, 2024
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Assignee:
SK hynix Inc., Icheon, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01); H10B 41/27 (2023.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 23/3171 (2013.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01);
Abstract
A method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region.