The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Dec. 28, 2022
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Ahmad R. Ansari, San Jose, CA (US);
John O'dwyer, Kildare, IE;
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 49/102 (2022.01); H04L 49/109 (2022.01); H04L 49/15 (2022.01);
U.S. Cl.
CPC ...
H04L 49/102 (2013.01); H04L 49/109 (2013.01); H04L 49/15 (2013.01);
Abstract
Embodiments herein describe an integrated circuit (IC) which includes a global ring that interconnects multiple local rings distributed throughout the IC. In one embodiment, the global ring is connected to the local rings using respective switches. The global ring (and the switches) interconnect the local rings so that a node coupled to one of the local rings can communicate with a node connected to another local ring.
Ansari, Ahmad. (2026). Global system interconnect for an integrated circuit (U.S. Patent No. 12627617). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12627617
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile