The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Nov. 27, 2023
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Venkatesh Vinjamuri, Andhra Pradesh, IN;

Subba Reddy Kallam, Austin, TX (US);

Atul Suresh Joshi, Maharashtra, IN;

Venkata Siva Prasad Pulagam, Telangana, IN;

Satish Nallamalla, Telangana, IN;

Rahul Kumar Gurram, Telangana, IN;

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3242 (2013.01); H04L 9/0643 (2013.01); H04L 9/3239 (2013.01); H04L 2209/20 (2013.01);
Abstract

An embedded system includes hash message authentication code (HMAC) hardware. The HMAC hardware receives data in separate data transfers to compute a hash. The HMAC hardware receives data of unaligned lengths in at least one of the separate data transfers. The data of unaligned lengths includes fewer valid bytes than the transfer size. The HMAC hardware responds to a residue indication indicating valid bytes associated with the data transfer to fill in the residue from a subsequent data transfer. For each data transfer the HMAC hardware receives an indication of whether the data is final data or if more data will be transferred for computation of the hash. The embedded system loads a linear buffer directly from scatter buffers, which contain encrypted data from a network. Decrypted data in the linear buffer is sent to a host using a direct memory access (DMA) operation responsive to a host request.


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