The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Jun. 10, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jiri Stulemeijer, Heerlen, NL;

Bhushan Shanti Asuri, San Diego, CA (US);

Andre Isidoro Prata, Nijmegen, NL;

Evgeny Levitan, Haifa, IL;

Ariel Yaakov Sagi, Haifa, IL;

Ibrahim Ramez Chamas, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/04 (2006.01); H01Q 1/52 (2006.01);
U.S. Cl.
CPC ...
H04B 1/0475 (2013.01); H01Q 1/523 (2013.01); H04B 2001/0425 (2013.01);
Abstract

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus may include first transceiver hardware comprising: first processing logic configured to generate a first plurality of output streams associated with a first sub-array of antenna elements of an antenna array by applying a first inverse power-amplifier-to-antenna-array network (A-1) matrix to one or more first input streams; and a first plurality of digital predistortion (DPD) circuits that are apply first DPD to the first plurality of output streams. The apparatus may include second transceiver hardware comprising: second processing logic configured to generate a second plurality of output streams associated with a second sub-array of antenna elements of the antenna array by applying a second A-1 matrix to second one or more input streams, and a second plurality of DPD circuits configured to apply second DPD to the second plurality of output streams.


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