Electronic circuit optimizing timing of clock signals and data signals and delay method thereof

Abstract

An electronic circuit applied to communication between a controller and a memory array includes a timer and a delay-locked loop. The timer counts a counting time based on a selection signal generated by the controller to generate a first enable signal. The delay-locked loop delays an output clock signal by a delay time based on a clock signal generated by the controller and the first enable signal to generate the delay clock signal. When the controller performs a read operation on the memory array, the memory array outputs the output clock signal and a data signal. The controller samples the data signal using the delay clock signal.