Nonvolatile memory devices and methods of controlling wordline erase operations within sub-blocks of memory strings

Abstract

A nonvolatile memory device may include at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of sub-blocks arranged in the vertical direction, and each of the sub-blocks includes boundary word-lines adjacent to another sub-block and internal word-lines different from the boundary word-lines. The control circuit may be configured to control an erase operation by applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, and by applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop.