The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Aug. 22, 2023
Applicant:

Veevx, Inc., Mesa, AZ (US);

Inventors:

Doug Smith, Mesa, AZ (US);

Sushil Sakhare, Mesa, AZ (US);

Assignee:

Veevx, Inc., Mesa, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01);
Abstract

To increase read reliability margins in read-only MRAM arrays, a complimentary pair of MRAM cells includes a first MRAM cell having a first resistance value within a first 'high' resistance range Rand storing a logic “HI” value and a second “shorted” MRAM cell having a second resistance value within a second “minimal” resistance range Rand storing a logic “LO” value. During manufacture and testing, MRAM cells that are assigned logic “LO” values are permanently shorted prior to distribution such that they permanently exhibit resistance values within the second “minimal” resistance range R. When reading the values stored within the complimentary pair of MRAM cells, a differential sense amplifier applies a common reference current across the first MRAM cell and the second “shorted” MRAM cell; by shorting cells with logic “LO” values, a system can reliably read logic values stored within the read-only MRAM array.


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