The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Aug. 04, 2023
Applicant:
Hong Kong Haicun Technology Co., Limited, Kowloon, HK;
Inventor:
Guobiao Zhang, Corvallis, OR (US);
Assignee:
Hong Kong HaiCun Technology Co., Limited, Kowloon, HK;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 18/21 (2023.01); G06F 21/56 (2013.01); G06N 3/063 (2023.01); G10L 15/183 (2013.01); G10L 15/22 (2006.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/3001 (2013.01); G06F 13/4004 (2013.01); G06F 15/803 (2013.01); G06F 18/21 (2023.01); G06F 21/561 (2013.01); G10L 15/183 (2013.01); G10L 15/22 (2013.01); H10W 90/00 (2026.01); G06F 2221/034 (2013.01); H10W 90/20 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/752 (2026.01); H10W 90/792 (2026.01);
Abstract
A discrete three-dimensional (3-D) processor comprises a plurality of storage-processing units (SPU's), each of the SPU's comprising a non-memory circuit, at least a memory array and at least an off-die peripheral-circuit component thereof. The 3-D processor further comprises first and second dice. The first die comprises the memory arrays, whereas the second die comprises the non-memory circuit and the off-die peripheral-circuit component.