Nvme completion and interrupt

Abstract

Instead of having uncertainty when waiting on completions, utilize unordered input output memory write (UIOMWr) to ensure the completions of the write. Using UIOMWr, the data storage device will write the competitions to a host dynamic random access memory (DRAM). When the device receives an approval of the completion, the device knows that the write to the host DRAM was successful. The approval will trigger the device to have the message signaled interrupts extended (MSIx) send an interrupt request (IRQ) to the host. The IRQ will pass through the PCIe and will be received by the host CPU. The host CPU will then process any pending completions in the host DRAM. An MSIx tag can be added to the completion (at the UIOMWr TLP level) that is assigned to multiple submission queues (SQ). When the MSIx tag is received by the host and device, the host and device will know what information needs to be pulled to avoid the need for translation later on.