Quadrature error correction circuit and memory device having the same

Abstract

The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.