The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Dec. 11, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Darshan Kumar Nandanwar, Bangalore, IN;

Sanku Mukherjee, Bangalore, IN;

Arvind Garg, Bangalore, IN;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01);
Abstract

DRAM access timing may be controlled based on charge remaining in cells of a DRAM row. DRAM timing and thus latency may be reduced in instances in which repeated row accesses are directed to the same row within an amount of time during which the row cell capacitances remain highly charged. In response to a row precharge, the row address may be stored in a table. Then, in response to a row activation and subsequent read/write access, a first timing parameter may be used in accessing the row when the row is in the table, and a second timing parameter may be used in accessing the row when the row is not in the table. Entries in the table may be periodically invalidated to reflect charge loss.


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