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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12622324 B1

PDFFull Text
Date of Patent:
May. 05, 2026

Filed:

Oct. 10, 2022

Semiconductor package and method for producing a semiconductor package

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Rainald Sander, Oberhaching, DE;

Lars Eckert, Neubiberg, DE;

Fortunato Lopez, Unterhaching, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:

Shumaker & Sieffert, P.A.

Primary Examiner:

Sue A Purvis

Assistant Examiner:

Jordan M Klein

Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 25/165 (2013.01); H01L 23/49575 (2013.01); H01L 24/48 (2013.01); H01L 2224/48245 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/182 (2013.01); H01L 2924/30101 (2013.01); H01L 2924/30107 (2013.01);
Abstract

A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.

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