The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Apr. 13, 2023
Applicant:

Oip Technology Pte Ltd., Singapore, SG;

Inventor:

Yonggang Jin, Singapore, SG;

Assignee:

OIP TECHNOLOGY PTE LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/13144 (2013.01);
Abstract

An interconnect structure for advanced packaging and method for the interconnect structure are disclosed. The method includes: providing a semiconductor substrate to be packaged having surface on which there is a first pad having conduction-promoting surface; depositing a first passivation layer on surface of the semiconductor substrate, the first pad is exposed from first passivation layer, forming a wiring layer on surface of the first passivation layer by screen printing, and forming a metal layer on surface of the wiring layer by electroless plating, wherein the wiring layer covers the first pad; forming a second passivation layer, which covers the first passivation layer and the interconnect, wherein there is a through hole in the second passivation layer, in which the metal layer is exposed; and forming a second pad by electroless plating, which fills the through hole and covers the second passivation layer around an opening of the through hole.


Find Patent Forward Citations

Quick Actions:

Jin, Yonggang. (2026). Interconnect structure for advanced packaging and method for the same (U.S. Patent No. 12622308). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12622308

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