The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Nov. 14, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaeryong Sim, Suwon-si, KR;

Donghyuck Jang, Hwaseong-si, KR;

Jeehoon Han, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02);
Abstract

Disclosed are 3D semiconductor memory device, electronic systems including the same, and methods of fabricating the same. The 3D semiconductor memory device includes lower selection lines extending in a first direction on a substrate and spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction, a middle stack structure including electrode layers and electrode interlayer dielectric layers that are alternately stacked on the lower selection lines, upper selection lines extending in the first direction on the middle stack structure and spaced apart from each other in the second direction, a first polishing stop layer disposed between the middle stack structure and the lower selection lines. The first polishing stop layer includes a material different from that of the electrode interlayer dielectric layers.


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