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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12621113 B1

PDFFull Text
Date of Patent:
May. 05, 2026

Filed:

Oct. 29, 2021

Sidelink interlace configuration

Applicant:

Lenovo (Singapore) Pte. Ltd., New Tech Park, SG;

Inventors:

Karthikeyan Ganesan, Kronberg im Taunus, DE;

Alexander Golitschek Edler Von Elbwart, Darmstadt, DE;

Vijay Nangia, Woodridge, IL (US);

Ankit Bhamri, Rödermark, DE;

Ali Ramadan Ali, Munich, DE;

Robin Thomas, Frankfurt am Main, DE;

Assignee:

Lenovo (Singapore) Pte. Ltd., Singapore, SG;

Attorney:

Kunzler Needham & Hilton

Primary Examiner:

Saad A Waqas

Int. Cl.
CPC ...
H04L 5/00 (2006.01); H04W 16/14 (2009.01); H04L 27/26 (2006.01);
U.S. Cl.
CPC ...
H04L 5/0094 (2013.01); H04L 5/0035 (2013.01); H04W 16/14 (2013.01); H04L 27/26025 (2021.01);
Abstract

Apparatuses, methods, and systems are disclosed for interlacing sidelink resources. One apparatus includes a transceiver and a processor that receives a resource pool configuration that indicates a subchannel size and resource pool time-frequency configuration for an unlicensed sidelink carrier and receives a corresponding interlacing configuration that indicates: the number of frequency resources per interlace based on the subchannel size, the spacing between the interlace based on the subchannel size, the minimum amount of resource to be used for transmission in a resource pool, and the type of interlacing to be performed. The transceiver transmits a sidelink channel according to the interlacing configuration within the unlicensed sidelink carrier.

Find Patent Forward Citations

Ganesan, Karthikeyan. (2026). Sidelink interlace configuration (U.S. Patent No. 12621113). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12621113

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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