The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Jan. 25, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Paul Nicholas Fletcher, Impington, GB;

Donghan Kim, Cambridge, GB;

Fei Tong, Bassingbourn, GB;

Ziming He, Barnet, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/04 (2006.01); H03F 1/32 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H04B 1/0475 (2013.01); H03F 1/3241 (2013.01); H03F 3/245 (2013.01); H03F 2200/451 (2013.01); H04B 2001/0408 (2013.01);
Abstract

A distortion apparatus for a power amplifier comprises: pre-distortion circuitry that comprises a memory polynomial look-up-table (LUT) circuit; and post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier. The pre-distortion circuitry comprises a plurality of LUTs. Each LUT corresponds to a different memory depth of a memory polynomial of a Volterra series. Each LUT indexed by an instantaneous power of an input sample delayed by an amount corresponds to a respective memory depth of each LUT. An output of the memory polynomial LUT circuit corresponds to a summation of an output of each LUT multiplied by the input sample delayed by the amount corresponding to the respective memory depth of each LUT, and an output of the pre-distortion circuitry is provided to the power amplifier.


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